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draft draft draft dr draft draft draft draf draft draft draft draft draft d draft draft draft draft draft draft dra 1. general description the UBA2072 is a low voltage ic intended to drive cold cathode fluorescent lamps (ccfls) for back-lighting applications. the ic contains level-shifters, bootstrap diodes and drivers for the external full-bridge power switches. furthermore, the UBA2072 has a build-in hf oscillator which determines the operating frequency, a phase shift controller for obtaining constant lamp current, and a pwm generator which is used to set the brightness level of the ccfls. the UBA2072 is designed to operate over a wide low voltage inverter supply range, up to 30v. the ic can be supplied directly from the inverter supply. 2. features wide supply voltage range (9 v to 30 v dc) adjustable maximum fault timing integrated level-shifters integrated bootstrap diodes lamp current control over-voltage control over-current protection ignition failure detection arcing detection brightness level adjustment through pwm dimming integrated pwm generator 3. applications lcd-backlighting, including lcd-tv and lcd-monitor applications. the ic is intended to drive and control a full-bridge inverter with resonant load circuit for ccfls, but can also drive an array of external electrode fluorescent lamps (eefls). UBA2072 low voltage full-bridge control ic for ccfl backlighting rev. 08.0 ?february 2007 preliminary data sheet
draft draft draft dr draft draft draft draf draft draft draft draft draft d draft draft draft draft draft draft dra UBA2072 ?nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 08.0 ?february 2007 2 of 28 nxp semiconductors UBA2072 low voltage full-bridge control ic for ccfl backlighting 4. ordering information 5. block diagram table 1: ordering information type number package name description version UBA2072t so28 plastic small outline package; 28 leads; body width 7.5 mm sot136-1 UBA2072ts ssop28 plastic shrink small outline package; 28 leads; body width 5.3 mm sot341-1 fig 1. block diagram UBA2072.
draft draft draft dr draft draft draft draf draft draft draft draft draft d draft draft draft draft draft draft dra UBA2072 ?nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 08.0 ?february 2007 3 of 28 nxp semiconductors UBA2072 low voltage full-bridge control ic for ccfl backlighting 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin assignment so28 and ssop28 package (top view) table 2: pin description symbol pin description function ifb 1 current feedback input. input signal for the lamp current control loop. should be connected to a voltage proportional to the lamp current. cifb 2 current regulation capacitor. a capacitor must be connected between this pin and the signal ground. it sets the time constant of the lamp current control loop. vfb 3 voltage feedback input input signal for the voltage control loop. should be connected to a voltage proportional to the transformer output voltage cvfb 4 voltage regulation capacitor a capacitor must be connected between this pin and the signal ground. it sets the time constant of the voltage control loop. iref 5 reference current output a 33k ? resistor must be connected between this pin and the signal ground. the ic uses it to make accurate internal currents. ct 6 fault timing capacitor a capacitor must be connected between this pin and the signal ground. it sets the time that a fault condition is allowed before the ic shuts itself down. sgnd 7 signal ground cf 8 hf-oscillator timing capacitor a capacitor must be connected between this pin and the signal ground. it sets the minimum switching frequency of the full bridge.
draft draft draft dr draft draft draft draf draft draft draft draft draft d draft draft draft draft draft draft dra UBA2072 ?nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 08.0 ?february 2007 4 of 28 nxp semiconductors UBA2072 low voltage full-bridge control ic for ccfl backlighting cswp 9 phase-shift sweep capacitor a capacitor must be connected between this pin and the signal ground. it sets the time in which the phase difference between bridge halve a and bridge halve b is swept down from regulation level to zero or swept up from zero to regulation level during pwm dimming. cpwm 10 pwm timing capacitor if a capacitor is connected between this pin and the signal ground, it sets the frequency of the pwm oscillator. if this pin is connected to signal ground the internal pwm oscillator is disabled. nc 11 not connected nonfault 12 status signal input/output the ic signals a fault condition to an external circuit by pulling this pin low and external circuits can also signal a fault condition to the ic by pulling this pin low. pwma 13 analog pwm dimming input the dutycycle of the internally generated pwm signal is proportional to the voltage on this pin. pmwd 14 digital pwm dimming input/output digital output of internally generated pwm signal if a capacitor is connected to the cpwm-pin. digital input of pwm signal if the cpwm-pin is connected to signal ground. note that the signal on the pwmd-pin is active low, so low voltage on the pwmd-pin means lamps are on. ghb 15 high-side driver output b gate connection of the high side power switch of full bridge halve b fsb 16 ?ating supply output b a buffer capacitor must be connected between this pin and the shb-pin. this capacitor is charged when the low side switch b is on and supplies the high side driver b. shb 17 high-side source connection b return for high side gate driver b. must be connected to the source of the high side power switch of full bridge halve b. nc 18 not connected en 19 chip enable input a low voltage on this pin will reset and shutt down the ic vdc 20 ic low-voltage supply input ic supply vdd 21 regulated 12 v supply output/input a buffer capacitor must be connected between this pin and power ground glb 22 low-side driver output b gate connection of the low side power switch of full bridge halve b pgnd 23 power ground return for low side drivers a and b gla 24 low-side driver output a gate connection of the low side power switch of full bridge halve a nc 25 not connected sha 26 high-side source connection a return for high side gate driver a. must be connected to the source of the high side power switch of full bridge halve a. fsa 27 ?ating supply output a a buffer capacitor must be connected between this pin and the sha-pin. this capacitor is charged when the low side switch a is on and supplies the high side driver a. gha 28 high-side driver output a gate connection of the high side power switch of full bridge halve a table 2: pin description ?ontinued symbol pin description function
draft draft draft dr draft draft draft draf draft draft draft draft draft d draft draft draft draft draft draft dra UBA2072 ?nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 08.0 ?february 2007 5 of 28 nxp semiconductors UBA2072 low voltage full-bridge control ic for ccfl backlighting 7. functional description the UBA2072 is designed to drive a full-bridge inverter with resonant load. the load consists typically of transformers with ccfls. two parameters are used by the UBA2072 to control the switches of the full-bridge inverter: the phase shift and the switching frequency. the two full bridge halves a and b ( figure 3 ) always operate at the same switching frequency. the frequency is used to control transformer output voltage during the ?st ignition of the lamps. the phase difference between the full-bridge halves a and b voltages (v a and v b ) controls the lamp current, as this determines the rms value of the full-bridge inverter voltage v a - v b ( figure 4 ). fig 3. full-bridge inverter de?ition fig 4. full-bridge inverter voltage and de?ition of phase shift
draft draft draft dr draft draft draft draf draft draft draft draft draft d draft draft draft draft draft draft dra UBA2072 ?nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 08.0 ?february 2007 6 of 28 nxp semiconductors UBA2072 low voltage full-bridge control ic for ccfl backlighting 7.1 ic supply the vdc pin is connected to an external supply with a voltage of 9 v to 30 v. the vdd-pin must be connected to a buffer capacitor (see figure 5 ). the vdd-pin acts as a regulated 12 v output, from which the gate drivers are supplied. external auxiliary circuits may also be supplied from the vdd pin. never supply the ic directly via the vdd-pin . vdc-pin voltage must always 1 be above vdd-pin voltage. 7.2 start-up and under-voltage lock-out (uvlo) the ic starts up at v vdc(start) and locks out (stops oscillating) when the voltage on the vdc-pin drops below v dc(stop) . 7.3 enable the UBA2072 is put in standby when the voltage on the en-pin comes below v en(low) (see t ab le 5 ). the ic will stop oscillating, and most of the internal circuits will shut down. however, the internal linear regulator between vdc and vdd will remain active, but with reduced current supply capability. all internal signals are reset when the en-pin is low. when the voltage on the en-pin comes above v en(high) the ic will start up again. 7.4 lamp (re-)ignition the ic starts at its maximum switching frequency f s(max) . first the capacitors at the cifb-pin and cswp-pin are charged (setting the phase shift between the two bridge halves to maximum). then the frequency is swept down to the minimum frequency f s(min) (see figure 7 ). during this initial ignition frequency sweep the lamp voltage will increase 1. during normal operation. during switch off faster fall down of vdc with respect to vdd is acceptable. fig 5. ic supply con?uration
draft draft draft dr draft draft draft draf draft draft draft draft draft d draft draft draft draft draft draft dra UBA2072 ?nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 08.0 ?february 2007 7 of 28 nxp semiconductors UBA2072 low voltage full-bridge control ic for ccfl backlighting as the frequency comes closer to the resonant frequency of the unloaded resonance circuit. once the ignition voltage v ign is reached, the lamps will ignite and the lamp voltage will drop to the voltage of the loaded resonance curve. advantage of the sweep rather then a xed ignition frequency is that sensitivity for spread in resonance frequency is much lower. once the lamps are ignited the frequency sweep down continues, gradually increasing the lamp current (the resonance circuit should now still be inductive, so current increases as frequency drops) untill the current regulation level is reached and the current regulation loop starts decreasing the phase shift between the bridge halves in order to keep the lamp current constant. if the current regulation loop cannot decrease the phase shift fast enough to counteract the frequency sweep down, then the frequency sweep is slowed down. once the frequency has reached fs(min), pwm dimming is enabled (see figure 7 ). initial ignition frequency sweep and pwm-generator are not synchronised, and once the frequency sweep is ?ished pwm dimming can start anywhere in its cycle. fig 6. initial ignition of ?urescent lamp via frequency sweep and load resonance .
draft draft draft dr draft draft draft draf draft draft draft draft draft d draft draft draft draft draft draft dra UBA2072 ?nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 08.0 ?february 2007 8 of 28 nxp semiconductors UBA2072 low voltage full-bridge control ic for ccfl backlighting during pwm dimming the switching frequency is constant. only the phase shift is swept from its regulated value to its minimum value and back. the phase shift sweep has to provide re-ignition of the lamps, therefor the unloaded resonance curve of figure 6 has to be high enough at the normal operation switching frequency fs(min). the voltage at the cvfb-pin is inverse proportional to the switching frequency,(see figure 8 ). the voltage at the cvfb-pin is clamped at the voltage v cvfb(range) were the switching frequency is fs(min). the voltage at the cswp-pin is proportional to the phase shift (see figure 8 ). the voltage at the cswp-pin is clamped at the low side at v cswp(lclamp) and at the high side at v cifb . because v cifb is clamped at v cifb(hclamp) , v cswp is also clamped. fig 7. timing diagram of the initial ignition frequency sweep fig 8. frequency and phase shift as function of cvfb and cswp voltages
draft draft draft dr draft draft draft draf draft draft draft draft draft d draft draft draft draft draft draft dra UBA2072 ?nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 08.0 ?february 2007 9 of 28 nxp semiconductors UBA2072 low voltage full-bridge control ic for ccfl backlighting 7.5 lamp current control the lamp current control is active during the initial ignition frequency sweep and when the lamps are on. it is disabled during the time within a pwm dim cycle that the lamps are off. an (ac or dc) voltage representing the lamp current, usually the voltage across an external sense resistor, is to be connected to the ifb-pin. this voltage is internally double-side recti?d (dsr), and compared to a reference level v ifb(reg) by an operational transconductance ampli?r (ota), as shown in figure 9 . when the current is being regulated, switches s1 and s2 (see figure 9 ) are closed (conducting). the output current of the ota is fed into capacitor c1, which is connected to the cifb-pin. the voltage across this capacitor is copied into capacitor c2, which is connected to the cswp-pin. the voltage on the cswp-pin controls the phase shift. 7.6 pwm dimming during the time within a pwm dim cycle that the lamps are off, switches s1 and s2 are opened (non-conducting). in this way the regulation level is stored in c1 when the current regulation loop is opened (see figure 9 ). after the regulation loop is opened, c2 is discharged (the voltage on the cswp-pin is swept down) to switch off the lamps, and charged again to turn the lamps on again. the lamps on versus off time is determined by the signal on the pwmd-pin (low = lamps on). the minimum phase difference between the bridge halves during the lamps off period of each pwm cycle is ? (min) . during the pwm lamps off period the phase shift level at which the lamp current was in regulation is preserved in the capacitor connected to the cifb-pin (c1 in figure 9 ). switches s1 and s2 are closed (conducting) again when the voltage on the cswp-pin has reached the voltage on the cifb-pin again. fig 9. lamp current control circuit
draft draft draft dr draft draft draft draf draft draft draft draft draft d draft draft draft draft draft draft dra UBA2072 ?nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 08.0 ?february 2007 10 of 28 nxp semiconductors UBA2072 low voltage full-bridge control ic for ccfl backlighting the phase shift sweep speed is determined by the capacitor connected to the cswp-pin (c2 in figure 9 ). the real lamp light output will be slightly less then the pwmd signal duty cycle because of the phase shift sweep time (see figure 10 ). when the lamp-on time is too short to sweep up the voltage on the cswp-pin, the ic will wait until the cswp voltage has actually reached the current control level before sweeping down again. this prevents that the lamps go out completely when deep dimming is combined with a too large capacitor at the cswp-pin. three pins are available to con?ure the internal pwm generator: the cpwm-, pwma-, and the pwmd-pin. the two possible pwm con?urations are shown in figure 11 . in the analog or master mode the internal pwm generator is active and generating the pwm signal. this signal is put on the pwmd-pin, which is automatically con?ured as an output. the minimum dutycycle of the internal pwm generator is limited to d pwm(min,intern) . when the cpwm-pin is connected to ground, the ic is put in digital or slave mode. the pwmd-pin is then an input and the ic uses the pwm signal provided on the pwmd-pin. the signal on the pwmd-pin is active low. a voltage below v pwmd(low) on the pin will turn the lamps on and a voltage above v pwmd(high) will turn the lamps off. pwm dimming of multiple ics can be synchronised by con?uring one ic as master and the others as slaves and connecting all pwmd-pins together. pwm dimming is only enabled in normal mode, when no fault condition excists. the only exception is when an external detected fault condition is entered via the nonfault-pin, then pwm dimming remains active (see figure 13 ). fig 10. light output as function of pwma input voltage
draft draft draft dr draft draft draft draf draft draft draft draft draft d draft draft draft draft draft draft dra UBA2072 ?nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 08.0 ?february 2007 11 of 28 nxp semiconductors UBA2072 low voltage full-bridge control ic for ccfl backlighting 7.7 the fault timer the fault timer provides a delay inbetween the detection of a fault and the shut down of the ic (enter stop-state). its time t fault(timeout) is proportional to the capacitor connected to the ct-pin. any fault condition will start the timer. when the timer is activated, the capacitor at the ct-pin will be alternatingly charged and discharged (see figure 12 ). these cycles are being counted by a four bit counter. after one cycle (the fault signalling delay t fault(delay) ) the nonfault-pin is activated (pulled low), to signal to any external circuit that there is a fault detected and the ic will stop if that fault continues. after 15 cycles is the fault time-out period t fault(timeout) reached, and the ic will enter stop-state. if the fault timer is inactive, the ct-pin voltage is one vbe ( ? 0.7v). the ct-timer has a protection that prevents the ic to start-up if the ct-pin is shorted to gnd. fig 11. pwm dimming con?urations fig 12. fault timer wavefporms
draft draft draft dr draft draft draft draf draft draft draft draft draft d draft draft draft draft draft draft dra UBA2072 ?nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 08.0 ?february 2007 12 of 28 nxp semiconductors UBA2072 low voltage full-bridge control ic for ccfl backlighting 7.8 protections all fault conditions and how they are processed in the ic can be found in figure 13 . the UBA2072 includes internal over voltage (ov), overcurrent (oc), bad contact or arcing (arc) and ignition failure (if) protections. there is also one pin (the nonfault-pin) which provides bidirectional fault signalling to and from any external circuit. via this pin a lamp short detection or over temperature detection or such can be added. in the next sections each fault protection function will be explained. 7.8.1 over voltage protection the over voltage protection circuit is intended to prevent the transformer output voltage from exceeding its maximum rating. it can also be used to regulate the output voltage to the required lamp ignition voltage. when the voltage on the vfb-pin exceeds the ov reference level v vfb(ovref) , over voltage is detected. as result pwm dimming is disabled and the fault timer is started. also the capacitor connected to the cvfb-pin is discharged (by i cvfb(ov) ). when the voltage at the vfb-pin drops below the ov reference level, the cvfb capacitor is charged (by i cvfb(charge) ) again.and the output voltage of the transformer will increase again. because the charging and discharging of the cvfb capacitor follows the ripple on the vfb voltage, the feedback gain of the voltage control loop is set by the ripple on the feedback signal. if cvfb is more discharged then charged (over a hf cycle) then the cvfb voltage will drop, and the switching frequency increase. as a result the output voltage of the transformer will decrease 2 . when this happens the current control loop is froozen (switch s1 of figure 9 is opened (non-conducting), so the regulation level stored in c1 cannot be changed by the current regulation loop) in order to prevent the frequency increase being compensated by a phase shift difference increase by the current control. fig 13. simpli?d control schematic. 2. presuming that the effective full bridge load impedance is in inductive region.
draft draft draft dr draft draft draft draf draft draft draft draft draft d draft draft draft draft draft draft dra UBA2072 ?nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 08.0 ?february 2007 13 of 28 nxp semiconductors UBA2072 low voltage full-bridge control ic for ccfl backlighting an internal latch makes the ov fault signal continuesly high even if the voltage at the vfb-pin only exceeds vvfb(ovref) during part of the output period. so the peak of the voltage on the vfb-pin determines if an over voltage fault condition is seen.in order to avoid that ov fault condition at the nominal switching frequency (with the lamps operating normally), the voltage ripple on the vfb-pin must not be too large. the voltage at cvfb is limited by the oscillator circuit to v cvfb(range) when the minimum switching frequency f s(min) is reached. this ensures an immediate frequency increase capability at over voltage detection. 7.8.2 over current detection when the absolute value 3 of the voltage across the current sense resistor (connected to the ifb-pin) exceeds the oc reference level v ifb(ocref) , over-current is detected. as result pwm dimming is disabled and the fault timer is started. 7.8.3 arcing detection if arcing occurs, for instance due to a bad lamp connection, it causes repetitive short current spikes that can be seen as voltage spikes at the ifb input 4 . the arcing detection circuit is directly connected to the ifb-pin, so it can only see spikes with a positive polarity. usually that will be suf?ient. it can detect spikes with amplitude above v ifb(arcref) and a duration longer then t spike(min) . each spike will trigger an internal one-shot, which signals to the control circuits that arcing has been detected. if this happens pwm dimming is disabled, and the fault timer is started. 7.8.4 ignition failure (if) when the current control loop comes close to its regulation point, the lamps are presumed to be on (ignited). this is when the average double side recti?d ifb-pin voltage is above v ifb(lampon) . if the lamps are not on when the ignition sweep is ?ished (switching frequency has reached f s(min) ), then an ignition failure is detected, pwm dimming is disabled and the fault timer is started. 7.8.5 the nonfault-pin the nonfault-pin provides bidirectional signalling of the fault status between the ic and any external circuit. when no fault is detected, the voltage on the pin is pulled high by an internal current source. an external circuit can signal to the ic that a fault has been detected by pulling down the pin. the ic will detect the current drawn from the pin and start the fault timer. to prevent interference with the pwm dimming, the ic will only look at the nonfault pin during the period that the lamp current regulation loop is closed (vcswp=vcifb). when the ic detects a fault internal (as in section 7.8.1 to section 7.8.4 ), it signals this via the nonfault pin by pulling the pin down. in this case the ic can not see anymore if theres an external detected fault, but thats no problem, because the faulttimer is then already running. 3. the oc comparator is behind the double side recti?r at the ifb-pin 4. provided that the current sensing circuit is simple sense resistor only.
draft draft draft dr draft draft draft draf draft draft draft draft draft d draft draft draft draft draft draft dra UBA2072 ?nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 08.0 ?february 2007 14 of 28 nxp semiconductors UBA2072 low voltage full-bridge control ic for ccfl backlighting the signal from the ic is a voltage signal and the signal to the ic is a current signal. in this way a driving con?ct is prevented. also it leaves the possibility for the outside world to see the signal from the ic even while a fault condition is being signalled to the ic in the mean time, as illustrated in figure 15 . 7.9 high- and low-side drivers the four drivers are identical. the output of each driver is connected to the equivalent gate of an external power mosfet. the bootstrap capacitors are charged from the vdd voltage when the low-side power mosfets are turned on, and they supply the high-side drivers. the vdd voltage directly supplies the low-side drivers. current sourcing capability and the on-resistance of the drivers can be found in t ab le 5 . fig 14. input and output levels at the nonfault pin. fig 15. splitting the nonfault pin signals to and from the ic.
draft draft draft dr draft draft draft draf draft draft draft draft draft d draft draft draft draft draft draft dra UBA2072 ?nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 08.0 ?february 2007 15 of 28 nxp semiconductors UBA2072 low voltage full-bridge control ic for ccfl backlighting 7.10 non overlap for each half bridge a delay is made between the switching-off of the external high side power transistor and the switching-on of the external low side power transistor and the other way round. the duration is the so called ?on-overlap?time (t nonov ). 8. limiting values table 3: limiting values in accordance with the absolute maximum rating system (iec 60134). all voltages are measured with respect to signal ground (pin 7); positive currents ?w into the chip. the voltage ratings are valid provided other ratings are not violated. symbol parameter conditions min max unit general r iref reference resistor value on pin iref 30 36 k ? sr slew rate on pins fsa, fsb, gha, ghb, sha, and shb ? 4 +4 v/ns t amb ambient temperature ? 25 +100 c t j junction temperature ? 25 +125 c t stg storage temperature ? 55 +150 c voltages v sha , v shb voltage on pins sha and shb 0 +30 v v fsa , v fsb voltage on pins fsa and fsb with respect to v sha , v shb -0.3 +14 v v en voltage on pin en -0.3 +14 v v gla , v glb voltage on pins gla and glb -0.3 v vdd v v gha voltage on pins gha v sha -0.3 v fsa v v ghb voltage on pins ghb v shb -0.3 v fsb v v pgnd voltage on pin pgnd 0 0 v v vdc voltage on pin vdc -0.3 +30 v v pwma , v pwmd , v nonfault voltage on pins pwma, pwmd and nonfault -0.1 +5 v v vfb voltage on pin vfb continuous -0.1 +5 v t<1ms -0.1 +8 v v ifb voltage on pin ifb continuous -5 +5 v t<100 s-9+9v esd
draft draft draft dr draft draft draft draf draft draft draft draft draft d draft draft draft draft draft draft dra UBA2072 ?nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 08.0 ?february 2007 16 of 28 nxp semiconductors UBA2072 low voltage full-bridge control ic for ccfl backlighting 9. thermal characteristics 10. characteristics v esd electrostatic discharge voltage human body model ifb, cifb, vfb, cvfb, iref, ct, cf, cswp, cpwm, nonfault, pwma, pwmd, en, vdc, vdd, gla, glb -2 +2 kv ghb, fsb, shb, sha, fsa, gha -1 +1 kv machine model all pins -250 +250 v latchup snw-fq-303 all pins table 3: limiting values ?ontinued in accordance with the absolute maximum rating system (iec 60134). all voltages are measured with respect to signal ground (pin 7); positive currents ?w into the chip. the voltage ratings are valid provided other ratings are not violated. symbol parameter conditions min max unit table 4: thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient in free air; so28 package 68 k/w in free air; ssop28 package 108 k/w table 5: characteristics t amb =25 c; v vdc = 15 v; v en =v vdd ; c vdd =100nf; r iref = 33 k ? and cpwm pin connected to a capacitor, unless otherwise speci?d. all voltages are measured with respect to signal ground (pin 7); currents are positive when ?wing into the ic. symbol parameter conditions min typ max unit start-up v vdc(start) start-up voltage level 8.6 9 9.4 v v vdc(stop) stop voltage level 7.7 8 8.3 v v vdc(hys) start-stop hysteresis level 0.9 1 1.1 v supply i vdc(on) total supply current on pin vdc oscillating [1] 5ma i vdc(on) total supply current on pin vdc vdc=30v; oscillating [1] 7.5 ma i vdc(off) total supply current on pin vdc v en =0v 1.5 ma i vdc(off) total supply current on pin vdc vdc=30v; v en =0v 2 ma v vdd(reg) regulated voltage on pin vdd vdc=30v; v en =0v 11.3 12 12.7 v v vdd(reg) regulated voltage on pin vdd at maximum supply current non-oscillating; i vdd =-36ma 11 v v vdc -v vdd dropout voltage vdd regulator vdc=10v; oscillating; [1] 1.5 v v boot voltage drop bootstrap diode i fsa = i fsb = 5ma 1.5 v ignition f s(max) / f s(min) vco frequency ratio 2.2 2.4 2.6 v cvfb(range) vco voltage range 2.5 v i cvfb(charge) cvfb charge current v vfb =2v, v cvfb =2v -24 -21 -18 a
draft draft draft dr draft draft draft draf draft draft draft draft draft d draft draft draft draft draft draft dra UBA2072 ?nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 08.0 ?february 2007 17 of 28 nxp semiconductors UBA2072 low voltage full-bridge control ic for ccfl backlighting normal operation f s(min) minimum switching frequency c cf = 100 pf 43.0 44.8 46.6 khz f s(min) minimum switching frequency 10 100 khz v ifb(reg) current regulation reference level 1.24 1.32 1.40 v v ifb(min) minimum voltage of lineair operating range - 2.5 v v ifb(max) maximum voltage of linear operating range 2.5 v r ifb input impedance ifb pin v ifb = 1v 40 k ? r ifb input impedance ifb pin v ifb = -1v 20 k ? k ifb transconductance ota 13 16 19 a/v drivers i driver(source) sourcing current of drivers v gla , v glb , v gha , v ghb = 1v, v vdd = v fsa = v fsb =12v -180 -145 -110 ma r driver(sink) sinking resistance of drivers v gla , v glb , v gha , v ghb = 1v, v vdd = v fsa = v fsb =12v 7.3 ? t nonov non-overlap time 0.45 0.55 0.65 s pwm dimming f pwm pwm frequency 100 1000 hz f pwm pwm frequency c cpwm = 33 nf 308 324 340 hz ? (min) minimum phase shift 0 o ? (max) maximum phase shift 180 o v cswp(low) cswp voltage resulting in ? (min) 1v v cswp(high) cswp voltage resulting in ? (max) 3v v cifb(hclamp) high cifb clamp voltage 3.1 v v cswp(lclamp) low cswp clamp voltage 0.95 v i cswp(charge) cswp charge current -24 -21 -18 a i cswp(discharge) cswp discharge current 18 21 24 a r pwma input impedance pwma pin 100 k ? v pwma(min) input voltage on pwma pin for minimum pwm duty cycle 1.24 v v pwma(max) input voltage on pwma pin for maximum pwm duty cycle 3v d pwm(min,intern) minimum pwm duty cycle [2] 12 % d pwm(min,extern) minimum pwm duty cycle cpwm pin connected to sgnd [2] 0% d pwm(max) maximum pwm duty cycle [2] 100 % i pwmd(source) source capability pwmd output v pwmd =3v -1 ma i pwmd(sink) sink capability pwmd output v pwmd =1v 1 ma table 5: characteristics ?ontinued t amb =25 c; v vdc = 15 v; v en =v vdd ; c vdd =100nf; r iref = 33 k ? and cpwm pin connected to a capacitor, unless otherwise speci?d. all voltages are measured with respect to signal ground (pin 7); currents are positive when ?wing into the ic. symbol parameter conditions min typ max unit
draft draft draft dr draft draft draft draf draft draft draft draft draft d draft draft draft draft draft draft dra UBA2072 ?nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 08.0 ?february 2007 18 of 28 nxp semiconductors UBA2072 low voltage full-bridge control ic for ccfl backlighting [1] gla, glb, gha and ghb open. [2] pwmd is active low: a low level on the pwmd pin corresponds with lamps on. example: d pwm =20% means pmwd is during 20% of each cyle low and the lamps are 20% of the time on, resulting in een light output of 20%. 11. application information figure 16 shows an example backlighting con?uration, where the inverter and the ic are supplied from the same dc voltage. two lamp are connected, each to another output of the same transformer. the leakage inductances of this transformer provides the ballast impedances for the lamp. an analogue voltage is converted to a pwm signal to provide for the desired brightness level. optional lamp short detection is via the lamp voltage sensing and d13, d23 and the nonfault-pin is indicated. v pwmd(high) logic high input level on pwmd 1.7 v v pwmd(low) logic low input level onpwmd 0.85 v protections v vfb(ovref) over voltage reference level 2.40 2.52 2.64 v i cvfb(ov) cvfb discharge current v vfb >v vfb(ovref) , v cvfb =2v 18 21 24 a v ifb(lampon) lamp on detection level 0.9 v v ifb(ocref) over current reference level 2.65 3.0 3.3 v v ifb(arcref) minimum detectable arcing spike amplitude 5v t spike(min) minimum detectable arcing spike duration 200 ns t fault(delay) fault output delay time c ct = 100 nf 0.063 0.069 0.075 s t fault(stop) fault stop time c ct = 100 nf 0.85 0.95 1.05 s v nonfault(open) open pin voltage on nonfault 4.7 5.0 5.3 v v nonfault(trigger) input trigger voltage on pin nonfault 3.8 4.3 4.8 v i nonfault(trigger) input trigger current of nonfault pin -32 -27 -22 a i nonfault(3v) low input nonfault pin current v nonfault = 3v -220 -190 -160 a i nonfault(short) short circuit current on pin nonfault v nonfault = 0v -240 -210 -180 a i nonfault(sink) maximum low output current on pin nonfault v nonfault = 1v 0.75 1 1.5 ma chip enable levels v en(high) logic high level on pin en 1.7 v v en(low) logic low level on pin en 0.9 v table 5: characteristics ?ontinued t amb =25 c; v vdc = 15 v; v en =v vdd ; c vdd =100nf; r iref = 33 k ? and cpwm pin connected to a capacitor, unless otherwise speci?d. all voltages are measured with respect to signal ground (pin 7); currents are positive when ?wing into the ic. symbol parameter conditions min typ max unit
draft draft draft dr draft draft draft draf draft draft draft draft draft d draft draft draft draft draft draft dra UBA2072 ?nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 08.0 ?february 2007 19 of 28 nxp semiconductors UBA2072 low voltage full-bridge control ic for ccfl backlighting fig 16. example backlighting application diagram
draft draft draft dr draft draft draft draf draft draft draft draft draft d draft draft draft draft draft draft dra UBA2072 ?nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 08.0 ?february 2007 20 of 28 nxp semiconductors UBA2072 low voltage full-bridge control ic for ccfl backlighting 12. test information 12.1 quality information the general quality speci?ation for integrated circuits, snw-fq-611 is applicable.
draft draft draft dr draft draft draft draf draft draft draft draft draft d draft draft draft draft draft draft dra UBA2072 ?nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 08.0 ?february 2007 21 of 28 nxp semiconductors UBA2072 low voltage full-bridge control ic for ccfl backlighting 13. package outline fig 17. package outline so28 (sot136-1)
draft draft draft dr draft draft draft draf draft draft draft draft draft d draft draft draft draft draft draft dra UBA2072 ?nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 08.0 ?february 2007 22 of 28 nxp semiconductors UBA2072 low voltage full-bridge control ic for ccfl backlighting fig 18. package outline ssop28 (sot341-1)
draft draft draft dr draft draft draft draf draft draft draft draft draft d draft draft draft draft draft draft dra UBA2072 ?nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 08.0 ?february 2007 23 of 28 nxp semiconductors UBA2072 low voltage full-bridge control ic for ccfl backlighting 14. soldering 14.1 introduction this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?e pitch smds. in these situations re?w soldering is recommended. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. 14.2 through-hole mount packages 14.2.1 soldering by dipping or by solder wave typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the speci?d maximum storage temperature (t stg(max) ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 14.2.2 manual soldering apply the soldering iron (24 v or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. 14.3 surface mount packages 14.3.1 re?w soldering re?w soldering requires solder paste (a suspension of ?e solder particles, ?x and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for re?wing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical re?w peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: below 225 c (snpb process) or below 245 c (pb-free process) for all the bga and ssop-t packages
draft draft draft dr draft draft draft draf draft draft draft draft draft d draft draft draft draft draft draft dra UBA2072 ?nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 08.0 ?february 2007 24 of 28 nxp semiconductors UBA2072 low voltage full-bridge control ic for ccfl backlighting for packages with a thickness 2.5 mm for packages with a thickness < 2.5 mm and a volume 350 mm 3 so called thick/large packages. below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 14.3.2 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?ally developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?ed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?x will eliminate the need for removal of corrosive residues in most applications. 14.3.3 manual soldering fix the component by ?st soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?t part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
draft draft draft dr draft draft draft draf draft draft draft draft draft d draft draft draft draft draft draft dra UBA2072 ?nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 08.0 ?february 2007 25 of 28 nxp semiconductors UBA2072 low voltage full-bridge control ic for ccfl backlighting 14.4 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?e. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . [3] for sdip packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. [4] hot bar soldering or manual soldering is suitable for pmfp packages. [5] these transparent plastic packages are extremely sensitive to re?w soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?w soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?w oven. the package body peak temperature must be kept as low as possible. [6] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [7] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [8] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?itely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [9] wave soldering is suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?itely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. table 6. suitability of ic packages for wave, re?w and dipping soldering methods mounting package [1] soldering method wave re?w [2] dipping through-hole mount dbs, dip, hdip, rdbs, sdip, sil suitable [3] ? suitable through-hole- surface mount pmfp [4] not suitable not suitable ? surface mount bga, lbga, lfbga, sqfp, ssop-t [5] , tfbga, vfbga not suitable suitable ? dhvqfn, hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable [6] suitable ? plcc [7] , so, soj suitable suitable ? lqfp, qfp, tqfp not recommended [7] [8] suitable ? ssop, tssop, vso, vssop not recommended [9] suitable ?
draft draft draft dr draft draft draft draf draft draft draft draft draft d draft draft draft draft draft draft dra UBA2072 ?nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 08.0 ?february 2007 26 of 28 nxp semiconductors UBA2072 low voltage full-bridge control ic for ccfl backlighting 15. revision history table 7: revision history document id release date data sheet status change notice order number supersedes UBA2072_1 2004 12 objective data - xxxx xxx xxxxx - UBA2072_2 2005 04 objective data - xxxx xxx xxxxx UBA2072_3 2005 04 objective data - xxxx xxx xxxxx UBA2072_4 2005 10 objective data - xxxx xxx xxxxx UBA2072_5 2006 04 objective data - xxxx xxx xxxxx UBA2072_6 2006 06 objective data - xxxx xxx xxxxx UBA2072_7 2006 08 preliminary data - xxxx xxx xxxxx UBA2072_8 2007 02 preliminary data - xxxx xxx xxxxx - - xxxx xxx xxxxx - xxxx xxx xxxxx - xxxx xxx xxxxx - xxxx xxx xxxxx - xxxx xxx xxxxx - xxxx xxx xxxxx
draft draft draft dr draft draft draft draf draft draft draft draft draft d draft draft draft draft draft draft dra UBA2072 ?nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 08.0 ?february 2007 27 of 28 nxp semiconductors UBA2072 low voltage full-bridge control ic for ccfl backlighting 15.1 data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 15.2 de?itions short-form speci?ation the data in a short-form speci?ation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?ition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?ation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?d use without further testing or modi?ation. 15.3 disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status ?roduction?, relevant changes will be communicated via a customer product/process change noti?ation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?d. 16. trademarks 16.1 contact information for additional information, please visit: http://www .nxp.com for sales of?e addresses, send an email to: sales.ad dresses@www .nxp.com level data sheet status [1] product status [2] [3] de?ition i objective data development this data sheet contains data from the objective speci?ation for product development. philips semiconductors reserves the right to change the speci?ation in any manner without notice. ii preliminary data quali?ation this data sheet contains data from the preliminary speci?ation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?ation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?ation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?ation (cpcn).
draft draft draft dr draft draft draft draf draft draft draft draft draft d draft draft draft draft draft draft dra UBA2072 ?nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 08.0 ?february 2007 28 of 28 nxp semiconductors UBA2072 low voltage full-bridge control ic for ccfl backlighting 17. contents

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